Overview of Device Physics Research
Device Physics Laboratory
Evolution of information technology is based on semiconductor devices of ultrahigh speed, low power dissipation, and ultrahigh density. The ultimate goal of silicon integrated system will be the control of a single electron in device functioning and control of a single atom in the fabrication process. Towards single electron control, we are proceeding with research on single electron transistors, single hole transfer devices, nanofabrication processes required for production of nano-scaled devices, and modeling of the Si oxidation process. Towards single atom control, we are developing a new approach of wafer-scale integration of self-organized nanostructures based on surface structure control. As a common basis for these goals, we are investigating new techniques for characterization of materials and device structures.
The single electron transistor is a device whose power dissipation is expected to be the minimum possible. We have already succeeded in fabricating an inverter that is a basic logic circuit element. In 2000, we fabricated an adder using our single electron transistors and demonstrated its operation. In addition to single electron circuits, we invented a single hole transfer device that is completely unprecedented. In this device, electrons and holes are spatially separated and the transport of a single hole is detected by the electron current. The single electron transistor was also applied to a new multiple-valued memory. We proceeded with characterization of the inside structure of the single electron transistor using scanning electron microscopy and considered theoretically the mechanism of single electron operation.
The most important process in Si technology is thermal oxidation of Si. We have shown that oxidation behavior under various oxidation conditions can be interpreted by the universal model for thermal oxidation which was proposed by this laboratory.
Towards room temperature operation of single electron devices, we are developing nanofabrication processes including electron beam lithography and resist processes. In nano-scale devices, pattern formation without roughness is indispensable. We have clarified the roughness generation mechanism and developed a new resist which can form a pattern with a very small roughness.
Conventional semiconductor devices are fabricated using resist patterns that are transferred from masks. On the other hand the "bottom-up process", in which device structures are fabricated from atomic structures on the substrate surface, attracts much attention. Towards realization of this process, we are investigating wafer-scale control of atomic structures on silicon surfaces. The dynamics of atomic steps and reconstructed domains were analyzed using scanning electron microscopy and low-energy electron microscopy. In order to control the arrangement of self-organized nanostructures, we have developed a novel technique to control the strain distribution on silicon surfaces: oxide inclusions are used to generate strain. We investigated the growth mechanism of Ge nanowires on Si surfaces. A new technique to form functional nanoparticles on Si surfaces has been proposed. By way of new materials research, we have started research on the growth and characterization of carbon nanotubes. We have established a novel characterization technique to observe the atomic structure of semiconductor surfaces during vapor-phase growth. This technique was applied to the analysis of the reconstruction of InP surfaces in a hydrogen ambient.
[ Back ]