Device Physics Laboratory
Single-electron devices are quite suitable for multiple-valued logic, because the discreteness of the electronic charge in a Coulomb island can be directly related to multiple-valued operation. However, it is fairly difficult to construct the circuit only with single-electron devices because of their low voltage gain and the small applicable voltage. To solve this problem, we have proposed a hybrid device comprising a single-electron transistor (SET) and a MOSFET, and demonstrated the operation using devices fabricated by pattern-dependent oxidation (PADOX) process on a silicon-on-insulator (SOI) wafer.
The proposed device has a simple structure of a serially connected SET and MOSFET. A MOSFET is used to keep the SET drain voltage constant at a low enough value. As a result, the current flowing through the device is determined only by the SET input voltage; it is not affected by the output voltage. When the input and output terminals are shorted together, multipeak negative-differential-resistance is attained as two-terminal characteristics (Fig. 1). With a proper load device (a constant-current source in the case of Fig. 1), many stability points appear and these can be assigned to multiple-valued levels [1].
Figure 2 shows the input-output waveforms of a quantizer, which is a basic
component of multiple-valued logic. The input voltage is transferred to the
output terminal (V in Fig. 1) at the moment sampling pulses turn on the transfer-gate
MOSFET (not shown in Fig. 1), and then quantized to the nearest stability
point. We can see that the different voltage levels in the triangular wave
are clearly quantized to stability points a～f.
With the proposed device, extremely compact multiple-valued logic can be
constructed because circuit size is independent of the number of multiple-valued
levels due to the periodic nature of the SET input-output characteristics.
A new application field of single-electron devices can now be explored by
the multiple-valued logic, as illustrated by an n-bit flash A/D converter
whose size is proportional to n (in contrast to n2-1
for conventional implementation) and an ultrahigh-speed multiple-valued adder
without carry propagation [2].
[1] H. Inokawa et al., Appl. Phys. Lett. 79 (2001) 3618.
[2] H. Inokawa et al., International Electron Devices Meeting (IEDM) (2001) 147.
 |
 |
||||
|
|