Overview of Device Physics Research

Yasuo Takahashi
Device Physics Laboratory

 Large-scale device integration technologies, which have led to rapid progress in information processing on cellar phones and portable computers, face difficulties in further downsizing and power consumption. To overcome these problems and thereby achieve further growth of information processing, the Device Physics Laboratory conducts research on the fabrication of nanostructures and single electronics, which enable us to make small and ultimately low-power devices. There are two approaches to achieving nanostructures: one is to refine lithographic techniques (top-down approach), and the other is self-assembly based on the atomic structures of the substrate (bottom-up approach). We are also investigating other methods to create nanostructures, such as carbon nanotubes.
 The Si Nanodevice Research Group is investigating the operation mechanism of Si single-electron transistors (SETs) and their circuit applications, and is seeking to establish fabrication principles. We have already proposed and fabricated single-electron inverters, adders and multiple-valued logic circuits, and actually demonstrated their functions. We recently demonstrated that our Si SETs do not have any offset-charge problems, which are thought to be the most serious obstacles to the practical use of SETs. We have also succeeded in making a new type of single-electron pump that enables us to transfer just a single-electron at high temperature. To control the potential profile in nanostructure silicon suitable for SETs, the Si oxidation process is the most important. We have investigated the oxidation mechanism theoretically by first-principles calculations and clarified the fundamental oxidation process. We are also doing simulations based on the proposed oxidation principle.
 The Nanostructure Technology Research Group is investigating nanofabrication techniques based on the top-down approach and methods of evaluating the fabricated nanostructures. We have achieved ultrafine resist pattern formation by improving electron-beam lithography and optimizing resist materials and processing, and demonstrated the nanometer-scale resist patterns with a high aspect ratio by using a supercritical-fluid drying process. Recently, we clarified the origin of the line edge roughness of resist patterns, which is the most important issue in making fine patterns. By using the developed fine-pattern formation technologies, we have fabricated and demonstrated small Si SETs with a high operation temperature. We have also succeeded in making an ultrasmall four-point probe for conductance measurement of small structures.
 The Surface Science Research Group is investigating wafer-scale control of atomic structures and ordered nanostructure formation based on the bottom-up approach. We have demonstrated many kinds of self-assembled nanostructures formed on Si surface by controlling the alignment of the surface atoms and/or local stress accumulated in the surface. By using synchrotron radiation, we have also succeeded in in-situ observation of surface structures during crystal growth. We recently clarified the step bunching mechanism theoretically and proposed a new model for Ge-atom reconfiguration on the silicon surface, which are useful for controlling the ordered nanostructures. Our research on carbon nanotubes has led to a new growth technique using microwave plasma. We also succeeded in observing the electronic states of nanotubes by photoelectron spectroscopy and detecting the defects by infrared spectroscopy. We have also investigated various kinds of materials and succeeded in making ordered CdS nanostructures and InP nanowires.

[Previous] [Top] [Next]