Encapsulated Gate-All-Around InAs Nanowire Field-Effect Transistors

Satoshi Sasaki, Guoqiang Zhang*, Kouta Tateno*, Yuichi Harada,
Shiro Saito, Akira Fujiwara, Tetsuomi Sogawa*, and Koji Muraki
Physical Science Laboratory, *Optical Science Laboratory

　Semiconductor nanowires (NWs) are attracting growing interest as promising building blocks for the next generation of nanoelectronic devices. InAs NWs are of particular importance in view of application to high-speed, low-power-consumption field-effect transistors (FETs) due to their high intrinsic electron mobility. We fabricated InAs NW FETs with a gate-all-around (GAA) structure, which enables improved electrostatic control, by employing a novel two-step gate electrode formation method. The gate electrode overlaps the source/drain electrodes, leading to a dramatic increase in driving current as a result of reduced series resistance [1].
　InAs NWs are grown via the Au-catalyzed vapor-liquid-solid (VLS) mode in a MOVPE system. The as-grown NWs are conformally coated with 6 nm of Al₂O₃, used as high-k gate dielectric, via atomic layer deposition (ALD). The NWs are then transferred to another Si/SiO₂ substrate with a prepatterned Ti/Au lower gate electrode (Fig. 1). Source and drain Ohmic contact regions are defined by electron-beam lithography at both ends of the NW, followed by Ar plasma etching to remove the surface oxides, and deposition of Al without breaking vacuum. This way, Ohmic contacts with low resistance are obtained. The Al surface is then oxidized to form an Al₂O₃ insulator in order to ensure electrical isolation between the upper gate and the source/drain electrodes. Finally, the Ti/Au upper gate is deposited overlapping the source/drain electrodes, thus encapsulating the NW and realizing GAA structure.
　Figure 2 shows drain current I_d vs. drain voltage V_d characteristics for various gate voltages V_g, for a FET device with gate length L_g = 220 nm and NW diameter d = 70 nm. The device exhibits n-type FET operation with a threshold voltage of 0.39 V. Drain current normalized by the NW circumference, w = πd, is also shown. Normalized transconductance, g_m/w, is 0.55 S/mm at V_d = 0.5 V, which outperforms existing FETs with homogeneous InAs NW channels. These superb on-state properties are ascribed to improved electrostatic control by GAA structure and to the reduction in series resistance by the gate-overlap geometry.


Fig. 1. Schematic device structure (left) and scanning-electron microscope image (right) of the InAs NW FET.	Fig. 2. Output characteristics of the InAs NW FET at room temperature.