Fabrication Method for IC-Oriented Si Single-Electron Transistors

Yukinori Ono, Yasuo Takahashi, Kenji Yamazaki, Masao Nagase, and Katsumi Murase

Device Physics Laboratory

Single-electron devices are promising for future LSIs because of their potential for low power consumption. In order to make the best use of this merit, it is necessary to increase the packing density of the single-election devices. For logic LSIs, miniaturization and integration of single-electron transistors (SETs) is important. Although the operation temperature of SETs has increased remarkably for the past few years, and near-room-temperature operation has been demonstrated, no reports so far have focused on miniaturization and packing of such application-oriented SETs for integration.

To achieve these points, we developed a novel fabrication method for Si SETs, which we call Vertical Pattern-Dependent Oxidation (V-PADOX) [1]. V-PADOX enables us to form two single-electron islands, at the same time, in an extremely small area. This method exploits pattern-dependent oxidation [2], by which the single-electron islands and tunnel barriers for SETs are formed in a self-organized manner. The starting pattern of Si to be oxidized is modulated in the vertical direction (hence V-PADOX), and consists of a thin region under a fine trench and two thick regions sandwiching it [Fig. 1, left]. After the oxidation, a Si single-electron island is formed at each edge of the thin region, and the rest of the thin region is converted into SiO2 [Fig. 1, right]. This is because less oxidation occurs around the edges due to stress accumulation, which allows us to produce two tiny islands without the need for lithographic definition of the islands themselves. We have successfully observed the currents for both SETs in a test device (Fig. 2), and have demonstrated that each SET can be individually controlled [1].

Because V-PADOX can pack two SETs in a tiny (~ 60 nm ´ 60 nm) area, it is suitable for integration of complementary logic circuits such as CMOS-type single-electron inverters, which promises to lead to single-electron logic LSIs.

[1] Y. Ono et al., IEDM (1998) 123.

[2] Y. Takahashi et al., Electronics Lett. 31(1995) 136.

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