.This is my poster presentaion for SSDM2002 (The 2002 International Conference on Solid State Devices and Materials, 2002.9.18, Nagoya Congress Center, Nagoya, JAPAN).
Title:
Evaluation of Lattice Distortion with Nanometer Resolution in Si Single-electron Transistor
Authors:
M. Nagase, S. Horiguchi, A. Fujiwara, and Y. Takahashi
Contents:
[INTRODUCTION]
{Si-SET on SOI Substrate}
{Initial Structure of Single-Electron
Transistor}
[previous results in SSDM2001]
{Structure of Si-SET}
{3D Analysis of Embedded Si Nanostructure
of SET}
{Structure and Effective Potential Profile
in Si Wire}
{Dependence of Gate Capacitance of SET
on Length of Embedded Si Wire}
{Theoretical Model of SET}
[Results]
{Estimation of Distortion in Si Nano-wire
in SET}
{Micro-sampling of Embedded Si in SET}
{Si Lattice Image of Nano-wire in SET}
{Averaging of Image}
{Distribution of Lattice Spacing}
{Length of Single-electron Island}
If you have any question or comment, please mail to nagase.
HOME PAGE of NTT Basic Res. Labs.
upload :2003/2/6
------------------------------------
(c) NTT Basic Research Laboratories
------------------------------------